In deep sub-micron designs, the effect of wire capacitance on system performance is as important as, if not more so than, the gate delay. To accurately predict system performance, accurate extraction of resistance and capacitance parasitics is required. The capacitance of a wire is dependent not only on its length, width, and thickness, but also on the environment around the wire. The environment includes any adjacent or near wires and the substrate itself. As wire pitches become smaller, the effects on capacitance of adjacent lines can be as much as two times as compared to an isolated wire. It is therefore very important to take into account the environment of a wire when predicting its capacitance.
Historically, most chip-level capacitance extractors have used one of two methods to derive wire capacitance:
1) High level analysis based on gross assumptions about the amount of capacitance per length of wire. This method relies on an educated guess as to the amount of adjacent wire that might be present. This is sufficient when the environment of a conductor does not change significantly or when the capacitance of the interconnects is only a small contributor to the overall output load. PA1 2) Detailed shapes based analysis of the design environment surrounding the wire under consideration. This method is very computer intensive. Accurate total capacitance extraction of large chips is presently not feasible with this approach due to data volume and computer execution time.
Previous solutions in the second category are design shape based. They have to calculate and store a large number of geometric interacting shapes, creating a large computational burden and an immense amount of output. An example is Avant!'s LPE extraction. The Avant! extractor uses design shapes to calculate the capacitances based on overlap areas distances and perimeters. This requires a large amount of data to be stored and processed.
Another solution in the second category, pattern recognition, can also take advantage of the regular structure of global wires. But the recognition mechanism on design shapes is not as efficient and the intermediate storage requirements are much more severe. The tables are huge; the search and the generation is very time consuming. Pattern recognition solutions are accurate but cannot handle wire extraction for a complete chip. ARCADIA from EPIC takes this approach.
Now, with narrowly spaced five and six levels of metal, the overall wire capacitance is larger and varies by a factor of two depending upon neighboring wires. Effects of neighboring conductors have become the dominant contribution to the load in many critical nets and the hold time needed on many paths. Resolution of adjacencies becomes a critical part of accurate chip timing.
Therefore, method 1 is not a viable solution for these deep sub-micron technology designs because it doesn't take neighboring wires into account. Method 2 is not practical for large designs due to the data volume and computer execution time.